1. Field of the Invention
Generally, the invention relates to static random access memories (SRAMs). More specifically, the invention relates to multi-port SRAMs that include input read registers and output drive registers for controlling and monitoring binary state devices.
2. Description of the Related Art
Microprocessors and microcontrollers have become a ubiquitous part of everyday life. They can be found in virtually all types of products available today: from transportation and manufacturing equipment, to consumer electronics, household appliances and children's toys. Processors control and monitor all or part of the functionality of these products using their general-purpose input/output (GPI/O) connections. This control can typically include such things as turning binary devices on and off for functional signaling to an end-user (e.g., toggling light emitting diode power to indicate whether a product is on or off, etc.) and monitoring the state of binary devices for system oversight (e.g., checking switch state to see whether a certain product function has been selected).
However, the number of GPI/O connections available for any given microprocessor or microcontroller is limited by, among other factors, the physical size of the processor. As the system demands on the GPI/O connections increase in number, a system designer is forced to choose between competing demands, selecting some at the expense of others. If the system designer desires to facilitate more demands than a processor's GPI/O connections can accommodate, the system designer must include external circuitry or use external input/output (I/O) processors to handle the overflow or excess demands. Both of these I/O overflow solutions are time, space, power and cost inefficient.
Also used within the typical microcontroller system of today is a random access memory (RAM), particularly a static RAM, or SRAM. An SRAM is a type of read/write memory that holds its data, without external refresh, for as long as power is supplied to it. An SRAM is typically used as external cache memory for processors and controllers. Cache memory is commonly used to store and retrieve commands, instructions and/or data that are frequently needed or used by the processor. In some applications, an SRAM can also be used as the main memory of a processor. An SRAM capable of interfacing with multiple processors, for example as cache memory and/or main memory, is commonly known as a multi-port SRAM (e.g., a dual-port device interfaces with two processors, etc.).
FIG. 1 illustrates a typical block diagram for a system 100 with multiple processors that control and/or monitor binary state devices 190, among other functions, and that access a multi-port SRAM 150. As shown in FIG. 1, N processors 111-113 are each connected to N ports 121-123, respectively, of the multi-port SRAM 150. Each of the N processors 111-113 is further connected to a variety of binary state devices 190 using the processors' GPI/O connections (not shown). The typical command within a processor to control a binary state device is a read/write to the GPI/O port that is coupled to that device. As an example of a limitation of the system in FIG. 1, assume that there are nine binary state devices 190. Further assume that N equals 3 and that each of three processors 111-113 has three GPI/O connections. In this case, all nine of the binary state devices 190 can be controlled or monitored by the processors 111-113 (i.e., each of the three processors 111-113 can be connected to three of the nine binary state devices 190).
However, with continued reference to FIG. 1, consider a further example where the number of binary state devices 190 in the system 100 exceeds the cumulative number of GPI/O connections for all of the N processors 111-113 (e.g., N equals one, total number of GPI/O equals three and the number of devices equals four). In this example, either additional, external means for controlling and/or monitoring the excess device(s) must be added to system 100, or the excess device(s) must be eliminated from the system 100. As previously discussed, adding external circuitry, such as external input/output (I/O) processors, to system 100 for handling the excess device(s) is time, space, power and cost inefficient. Likewise, excluding a binary state device 190 from control by the processors 111-113 may not be an option based on customer demands and system requirements.
Thus, what is needed is an external means for one or more processors to control and/or monitor binary state devices without adding additional circuit elements to the processor-based system, thus freeing up or expanding the functionality of the processors' GPI/O connections.